1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof.
2. Description of the Related Art
In recent years, a MONOS structure provided with a stacked layer gate including a charge accumulation layer, a block layer, and a control gate is adopted in a memory cell of a NAND flash memory. A MOS structure is adopted in a peripheral circuit.
Therefore, when manufacture of the memory cell and manufacture of the peripheral circuit are attempted in the same step, since the peripheral circuit does not include the charge accumulation layer and the block layer, which is different from the memory cell, a difference in height between a transistor in the memory cell and a transistor in the peripheral circuit occurs.
There is generally polysilicon as material adopted as a control gate for the MONOS structure and a gate electrode in the MOS structure. For example, Jpn. Pat. Applin. KOKAI Publication No. 07-94731 describes that, since the polysilicon is high resistance value, reduction in its resistance can be realized by adopting such an approach as silicidation for causing a surface of the polysilicon to react with high melting point metal in view of low power consumption and speeding-up of an operation speed in a semiconductor memory device. A sufficient resistance value required could have been obtained by silicidation until now.
However, according to high resistance due to shrink of a memory cell and a gate electrode of a peripheral transistor, a sufficient resistance value cannot be obtained by only silicidation of a control gate. Further, as described above, since a height of the MONOS structure and the MOS structure is difference, when the control gate of a memory cell transistor is silicided, a gate of a peripheral transistor is only partially silicided. Even if the gate of a peripheral transistor is silicided, the composition of silicidation is difference. As a result, there is such a problem that operation reliability deteriorates.